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CCD Delay Line Series
MN38662S
NTSC-Compatible CCD Video Signal Delay Element
Overview
The MN38662S is a CCD signal delay element for video signal processing applications. It contains such components as a threefold-frequency circuit, a shift register clock driver, charge I/O blocks, two CCD analog shift registers switchable between 681 and 605 stages, a clamp bias circuit, resampling output amplifiers, and booster circuits. When the switch input is "L" level, the MN38662S samples the input using the supplied clock signal with a frequency of three times the NTSC color signal subcarrier frequency (3.579545 MHz) and, after adding in the attached filter delay, produces independent delays of 1 H (the horizontal scan period) each for the two lines.
MN38662S Datasheet
